Abstract—Miniaturization limitations and some show stoppers are

Abstract—Miniaturization has been a constant challenge to meet the demands of high performance, high density, low power and low voltage of complex devices. Miniaturization is the main driving force for the migration from micro electronic device structure to Nano electronic device structures. Planar CMOS scaling has been delivering better performance & low power devices at each cutting edge of the technology node for more than three decades. Now, CMOS scaling is facing crucial limitations and some show stoppers are affecting bulk CMOS scaling. So, semiconductor industry is witnessing the phase-out of Planar CMOS with the introduction of new device architecture like 3D FinFET technology for extending the Moore’s Law for Nanoscale technologies. This paper discusses the evolution of Planar CMOS technology, CMOS scaling challenges, Planar CMOS optimization technologies & the next generation Nano architectures in order to extend the scaling beyond planar CMOS. FinFET is emerging technology beyond 22nm. This paper studies FinFET architecture, advantages and manufacturing challenges associated with it. It also throws light on future technologies like Carbon nanotube, Silicon Nanowire FET and Tunneling FET etc.


Index Terms—FinFET, CMOS Scaling, FD-SOI, HKMG, Carbon nanotube, Nanowire FET, Tunneling FET.

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I.               Introduction

Semiconductor device industry has marched at the pace of Moore’s Law. The number of transistors doubles approximately every two years as a result of continuous scaling of transistors, which has been the distinct feature of the semiconductor manufacturing industry. Each newer generation technology produces more functionality, denser & faster transistors compared to previous generation technology 1.

The size of the transistor is decreasing continuously with the decrease in the thickness of the silicon dioxide gate dielectric to increase the gate capacitance and the drive current, which ultimately provides better device performance 14.  The ultra-scaled CMOS devices are facing challenges due to shrinking geometrics, less supply power, and higher frequencies demands, thereby causing short channel effect which increases the leakage currents in the device constantly. The enhancement in the scaling technology has increased the need of low power circuits 14. In Nano devices, CMOS based circuits are not used due to the problems like Short Channel Effect (SCE), high leakage thereby increasing static power 14. New technologies are needed for handling the various effects of CMOS scaling. The planar CMOS shows significant SCE and hence migration to new device structures with negligible SCE for the same channel length is getting significant attention.



FinFET have significantly captured the attention of the industry over past decade because of the degrading SCE of planar CMOS behaviour. In the planar MOSFET channel is horizontal whereas in FinFET channel is vertical known as Fin. Multiple fins and smaller fin heights leads to more flexibility and width of the channel can be increased, which in turn increases silicon area.


II. Evolution of IC Process technology

A. Bipolar Technology

     The first transistor was developed by John Bardeen, Walter Brattain and William Shockley at Bell laboratories in 1947 which enabled the rapid growth of the semiconductor technology industry. The first integrated circuits (IC) of seventies available in market has a few hundred transistors which were manufactured in bipolar technology 29. Bipolar transistors can be either of NPN or PNP structure. In these bipolar transistors, small current into very thin base region controls the large current between emitter and collector. Base currents limit significantly affects the integration density of these devices 29. Bipolar technology delivered high current drive, high switching speed, smaller delay, high performance, but high power consumption makes very large integration difficult.


B. MOSFET Technology

The Metal-Oxide-Semiconductor Field Effect Transistor commonly known as MOSFET was introduced with very attractive feature of low power consumption, low operating voltage, higher speed etc., which made it useful in electronic design 20. Two types of MOSFET structure namely P-MOSFET and N-MOSFET are used for designing integrated circuits. Unfortunately, both consumes high static power. Frank Wan lass introduced a new logic design known as CMOS using complementary PMOS and NMOS. The main advantage of CMOS technology includes high noise immunity and very low static power consumption. Since CMOS consumes very low power, it allows much higher level of integration because of which innovative CMOS device with excellent features were evident past several decades. The trends of CMOS integrated circuits downsizing are as given below 20.

(2D technology from 1970) 10µm-> 8 µm-> 6 µm -> 4 µm -> 3 µm -> 2 µm -> 1.2 µm -> 0. µm 8-> 0.5 µm -> 0.35 µm -> 0.25 µm -> 180nm->130nm-> 90nm-> 65nm-> 45nm-> 32nm-> 28nm->

(3D technology) -> 22nm (2011)-> 15nm (2013)-> 10nm (2015)-> 7nm (2017) 20.


C. BiCMOS Technology

Bipolar CMOS popularly known as BiCMOS technology integrates both CMOS and Bipolar technology on the same silicon substrate. CMOS offers high and symmetrical noise margin, high input impedance and low power consumption but for the speed constraint 29. In contrast, the Bipolar offers high drive current, high switching speed, smaller propagation delay, but very large scale integration is limited by its high power consumption. BiCMOS has made it possible to combine meritorious features of CMOS and Bipolar technology in a single process at reasonable cost to achieve the high density integration of CMOS with high current driving capability of bipolar transistors.